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JM20330 Datasheet Rev 3.0JMH330 Datasheet Rev 3.5Rohm BU29504KV Datasheet Rev 0.97SunPlus SPIF223A Datasheet
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Pin #NameTypeDescriptionNameTypeDescriptionNameTypeDescriptionNameTypeDescription
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22XTALIAICrystal Input/Oscillator Input. It is connected to a 25MHz crystal or crystal oscillator, frequency tolerance ±50ppm.XTALIAICrystal Input/Oscillator Input. It is connected to a 25MHz crystal or crystal oscillator, frequency tolerance ±50ppm.XTALIAICrystal Oscillation Circuit Input:
25MHz crystal oscillator shall be connected externally.		XTALI/CLKIICrystal oscillator input or external clock input
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23XTALOAOCrystal Output. It is connected to a crystal. While crystal oscillator is applied, this pin should be reserved as No Connection (NC).XTALOAOCrystal Output. It is connected to a crystal. While crystal oscillator is applied, this pin should be reserved as No Connection (NC).XTALOAOCrystal Oscillation Circuit OutputXTALOOCrystal oscillator output
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26REXTAIExternal Reference Resistance. An external 12KΩ1% (12.1 KΩ 1%) resistor should be connected and bypass to the analog ground. (Note 1)REXTAIExternal Reference Resistance. An external 12KΩ1% (12.1 KΩ 1%) resistor should be connected and bypass to the analog ground. (Note 1)REXTAIExternal Reference Resistor Connection Input:
As the reference, a resistor with 11.3/10KΩ should be connected to ground. The accuracy of resistor must be within ±1% (ref. Figure 8-1).		REXTIExternal reference resistor input
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27RXPAISerial Data Receiver. It receives positive input of differential signal.RXPAISerial Data Receiver. It receives positive input of differential signal.RXPAISerial Data Receiver:
Differential input signal: 1.5Gbps
Only AC connection shall be supported.		RXPIDifferential receive +ve
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28RXNAISerial Data Receiver. It receives negative input of differential signal.RXNAISerial Data Receiver. It receives negative input of differential signal.RXNAISerial Data Receiver:
Differential input signal: 1.5Gbps
Only AC connection shall be supported.		RXNIDifferential receive –ve
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32TXPAOSerial Data Transmitter. It transmits positive output of differential signal.TXPAOSerial Data Transmitter. It transmits positive output of differential signal.TXPAOSerial Data Transmitter:
Differential output signal: 1.5Gbps
Only AC connection shall be supported.		TXPODifferential transmit +ve
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31TXNAOSerial Data Transmitter. It transmits negative output of differential signal.TXNAOSerial Data Transmitter. It transmits negative output of differential signal.TXNAOSerial Data Transmitter:
Differential output signal: 1.5Gbps
Only AC connection shall be supported.		TXNODifferential transmit –ve
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61, 63, 1, 3, 6, 10, 12, 14, 15, 13, 11, 7, 5, 2, 64, 62DD[15:0]DIOData Bus. This is a bi-directional data bus for a host and a device to transfer data, command, and status.DD[15:0]DIOData Bus. This is a bi-directional data bus for a host and a device to transfer data, command, and status.DD[15:0]Pins 3 and 11 are DIOL

All others are DIO
ATA/ATAPI Data Bus:
ATA/ATAPI Bi-directional Data Bus.		B_IDE_DD[15:0]IOATA Interface Data Bus
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47,48CSn[1:0]DIOChip Select. Active-low signals from a host to select a Command Block or Control Block register of a device.CSn[1:0]DIOChip Select. Active-low signals from a host to select a Command Block or Control Block register of a device.CSn[1:0]DIOATA/ATAPI Chip Select:
[Host mode: In, Device mode: Out]
Chip select signal for the device register access.		IDE_CS[1:0]_BIOATA Interface Chip Select
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49, 51, 50DA[2:0]DIODevice Address. Address signals from a host to access a register or data port of the device.DA[2:0]DIODevice Address. Address signals from a host to access a register or data port of the device.DA[2:0]DIOATA/ATAPI Data Address:
[Host mode: In, Device mode: Out]
Address signal for data access.		IDE_DA[2:0]IOATA Interface Device Address
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58DIORn/
HDMARDYn/
HSTROBE		DIOIO Read/Ultra DMA Ready/Ultra DMA Data Strobe.
DIORn: Active-low signal from a host to read a register or data port of a device.
HDMARDYn: Active-low signal from a host to indicate its ready to receive Ultra DMA data-in burst from a device.
HSTROBE: Signal from a host to latch data into a device at Ultra DMA data-out operation.		DIORn/
HDMARDYn/
HSTROBE		DIOIO Read/Ultra DMA Ready/Ultra DMA Data Strobe.
DIORn: Active-low signal from a host to read a register or data port of a device.
HDMARDYn: Active-low signal from a host to indicate its ready to receive Ultra DMA data-in burst from a device.
HSTROBE: Signal from a host to latch data into a device at Ultra DMA data-out operation.		DIORn/
HDMARDYn/
HSTROBE		DIOIO Read / UDMA Ready / UDMA Data Strobe:
[Host mode: In, Device mode: Out]
- At UDMA transfer:
Functions as HDMARDYn (at reading) / HSTROBE (at writing) signal.
Notification signal for ‘Ready to Receive Data’ when reading.
Strobe signal for data latch timing when writing.
- Other than UDMA transfer:
Functions as DIORn. (Register data reading signal)		IDE_DIOR_BIOATA Interface I/O Read ATA Interface DMA Ready during Ultra DMA data-in bursts
ATA Interface Data Strobe during Ultra DMA data-out bursts
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59DIOWn/
STOP		DIOIO Write/Stop Ultra DMA Burst.
DIOWn: Active-low signal from a host to write a register or data port of a device.
STOP: Active-high signal from a host to terminate an Ultra DMA transfer.		DIOWn/
STOP		DIOIO Write/Stop Ultra DMA Burst.
DIOWn: Active-low signal from a host to write a register or data port of a device.
STOP: Active-high signal from a host to terminate an Ultra DMA transfer.		DIOWn/
STOP		DIOIO Write / UDMA Stop:
[Host mode: In, Device mode: Out]
- At UDMA transfer:
Functions as a STOP signal. (Data transfer stop requesting signal)
- Other than UDMA transfer:
Functions as DIOWn. (Register data writing signal)		IDE_DIOW_BIOATA Interface I/O Write ATA Interface Stop during Ultra DMA data bursts
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54DMACKnDIODMA Acknowledge. Active-low signal from a host to acknowledge the DMA request from a device.DMACKnDIODMA Acknowledge. Active-low signal from a host to acknowledge the DMA request from a device.DMACKnDIODMA Acknowledge:
[Host mode: In, Device mode: Out]
Used at DMA transfer. Answering signal for data transfer start which the Host responds to the DMARQ signal (60 pin) from the device side.		IDE_DMACK_BIOATA Interface DMA Acknowledge
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60DMARQDIODMA Request. Active-high signal from a device to request a DMA transfer.DMARQDIODMA Request. Active-high signal from a device to request a DMA transfer.DMARQDIOLDMA Request:
[Host mode: Out, Device mode: In]
Used at DMA transfer. Data transfer start requesting signal from the Device side to Host side.		IDE_DMARQIOATA Interface DMA Request
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53INTRQDIODevice Interrupt. Active-high signal from a device to interrupt a host.INTRQDIODevice Interrupt. Active-high signal from a device to interrupt a host.INTRQDIODevice Interrupt:
[Host mode: Out, Device mode: In]
Interruption requesting signal from the device side.		IDE_INTRQIOATA Interface Interrupt Request
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55IORDY/
DDMARDYn/
DSTROBE		DIOIO Ready/Ultra DMA Ready/Ultra DMA Data Strobe.
IORDY: Active-high signal from a device to extend the host cycle time for operation at PIO mode 3 and above.
DDMARDYn: Active-low signal from a device used to indicate its ready to receive Ultra DMA data-out burst from a host.
DSTROBE: Signal from a device used to latch data into a host at Ultra DMA data-in operation.		IORDY/
DDMARDYn/
DSTROBE		DIOIO Ready/Ultra DMA Ready/Ultra DMA Data Strobe.
IORDY: Active-high signal from a device to extend the host cycle time for operation at PIO mode 3 and above.
DDMARDYn: Active-low signal from a device used to indicate its ready to receive Ultra DMA data-out burst from a host.
DSTROBE: Signal from a device used to latch data into a host at Ultra DMA data-in operation.		IORDY/
DDMARDYn/
DSTROBE		DIOIORDY / DDMARDY / DSTROBE:
[Host mode: Out, Device mode: In]
- At UDMA transfer:
Functions as DDMARDYn (at writing)/DSTROBE (at reading) signal.
Notification signal for ‘Ready to Receive Data’ when writing.
Strobe signal for data latch timing when reading.
- Other then UDMA transfer:
Functions as IORDY signal. Wait requesting signal from the Device side.		IDE_IORDYIOATA Interface I/O Ready ATA Interface DMA Read during Ultra DMA data-out bursts ATA Interface Data Strobe during Ultra DMA data-in bursts
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46PDIAGn/
PATAOR		DIOHDiagnostic Signal.
In Host Bridge mode: PDIAGn provides the diagnostic signals from device 1 to device 0 to indicate the device 1 diagnosis is complete.
In Device mode: PATAOR defines the pin order of parallel ATA interface. (see 5.6)
0: ATA interface signals in Normal Order mode.
1: ATA interface signals in Reverse Order mode.		PDIAGn/
PATAOR		DIOHDiagnostic Signal.
PDIAGn provides the diagnostic signals from device 1 to device 0 to indicate the device 1 diagnosis is complete.		PDIAGnDIOHPass Diagnostics / Parallel ATA Bus Order Reverse:
- In the Host mode:
Functions as PDIAGn signal. Notification signal for the results of the self-diagnostic from Slave to Master.
- In the Device mode [Only valid for BU29504]:
Bus switching signal for the Parallel ATA (ref. Table 5-1).
0: ATA interface (in the Normal Order mode)
1: ATA interface (in the Reverse Order mode)
CBLID - No functionality		IDE_PDIAGIOATA Interface Passed Diagnostics ATA Interface Cable Assembly Type Identifier
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16RESETnDIOHardware Reset. Active-low signal from a host to reset a device.RESETnDIOHardware Reset. Active-low signal from a host to reset a device.RESETnDIOHardware Reset:
[Host mode: In, Device mode: Out]
Resetting signal from the Host to Device side (Active Low).		I_IDE_RST_BIOATA Interface Reset.
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34DASPnDIOHSlave Device Present. Active-low signal from Device 1 to Device 0 in Host Bridge mode to indicate the presence of slave device.
In Device 0: configuration, this pin is an input.
In Device 1: configuration, it is an output. This pin is used as slave present indicator at ATA power on device diagnostics phase, and used as device activity at command or data transfer.
In Device Bridge mode, the pin is output (reserved).		DASPnDIOHSlave Device Present. Active-low signal from Device 1 to Device 0 that indicate the presence of slave device.
In Device 0 configuration, this pin is an input.		DASPnDIOHSlave Present / Device Active
[In the Host mode only]
- At operating a reset protocol:
Functions as DASPn signal. (Present signal from the Slave to Master) [Active Low / Master: In, Slave: Out]
(Also refer to the MSSEL Signal Pin.)
- After operating the reset protocol:
Signal for Device Active indicator.		IDE_DASPIOATA Interface Device Active or Slave(Device 1) Present
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52SPDIOLSlave Device Present. Active-high signal from Device 1 to Device 0 in Host Bridge mode to indicate the presence of slave device.
In Device 0 configuration, this pin is an input.
In Device 1 configuration, it is an output.
In Device Bridge mode, SP is cable detection pin, default setting is used 80-conductor cable.
0: 80-conductor cable is detected.
1: 40-conductor cable is detected.		SPDILSpecial internal test Pin. No connect.SPDIOLSlave Present
[In the Host mode only]
Present signal from the Slave to Master.
Same functions as DASPn (34 pin). However, it operates as a present signal, except for the Reset protocol..
Mainly used when hot swapping is functioning.
[Active Hi (PHYRDY output) / Master: In, Slave: Out]
(Also refer to the MSSEL Signal Pin.)		IDE_CSELIOATA Interface Cable Select
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24AVDDHAIAnalog Power. Analog 3.3V power supply. It should be bypassed to ground by a 0.1uF capacitance.AVDDHAIAnalog Power. Analog 3.3V power supply. It should be bypassed to ground by a 0.1uF capacitance.AVDDHAI3.3V Analog Power SupplyVDDAPWR1.8V Analog Power
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29AVDDLAIAnalog Power. Analog 1.8V power supply. It should be bypassed to ground by a 0.1uF capacitance.AVDDLAIAnalog Power. Analog 1.8V power supply. It should be bypassed to ground by a 0.1uF capacitance.AVDDLAI1.8V / 1.2V (ref. Table 2-1) Analog power supplyVDDAPWR1.8V Analog Power
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25, 30AGNDAIAnalog GroundAGNDAIAnalog GroundAGNDAIAnalog GNDGNDAGNDAnalog Ground
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4, 44VCCODIDigital IO Power. Digital 3.3V power supply. It should be bypassed to ground by a 0.1uF capacitance.VCCODIDigital IO Power. Digital 3.3V power supply. It should be bypassed to ground by a 0.1uF capacitance.VCCODI3.3V I/O Power SupplyD3V3_IOPWR3.3V Digital I/O Power
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9VCCKDIDigital Core Power. Digital 1.8V power supply. It should be bypassed to ground by a 0.1uF capacitance.VCCKDIDigital Core Power. Digital 1.8V power supply. It should be bypassed to ground by a 0.1uF capacitance.VCCKDI1.8V / 1.2V (ref. Table 2-1) Core power supplyD1V8_COPWR1.8V Digital CORE Power
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56D3V3_IOPWR3.3V Digital I/O Power
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8, 42, 57DGNDDIDigital ground.DGNDDIDigital ground.DGNDDIDigital GNDDVSSGNDGround for the Digital Core and I/O
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17PORnDIHPower On Reset. Low-active global reset. It should be connected to an external RC to build the power on initialization.PORnDIHPower On Reset. Low-active global reset. It should be connected to an external RC to build the power on initialization.PORnDIHPower On Reset:
Chip resetting signal (Active Low).		RESET_BIASIC Reset input
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35SSCENDILSpread Spectrum Clock Enable.
0: Disable SATA spread spectrum clocking. (default)
1: Enable SATA spread spectrum clocking.		RSVDLDILReserved pin, it must be set to low.SSCENDILSpread Spectrum Clock Enable:
Control signal for spread spectrum clock function.
0: Invalidate the spread spectrum clock function (default).
1: validate the spread spectrum clock function.		IDE_JUMP1IJumper 1
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37CLKSEL[1:0]DILReference Clock Selection.
01: 25MHz external reference clock.
others: reserved.		CLKSEL[1:0]DILReference Clock Selection.
01: 25MHz external reference clock.
others: reserved.		CLKSEL[1:0]DILReference Clock Selection:
Frequency setting for crystal oscillator.
01: 25MHz external crystal oscillator (default).
Others: Reserved.		UAO_SPI_OUTOUART/SPI data output
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36DIHDIHDIHTEST_CFGITest Configuration bit 0
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40PHYRDYDOPhysical Layer Ready.
0: Serial ATA physical layer communication is not established.
1: Serial ATA physical layer communication is established.		PHYRDYDOPhysical Layer Ready.
0: Serial ATA physical layer communication is not established.
1: Serial ATA physical layer communication is established.		PHYRDYDOLPhysical Layer Ready:
Communication establishment signal after completion of an initialization for the Serial ATA PHY layer.
0: Right after POR or when initialization failed for the Physical layer.
1: Initialization for the PHY layer has completed.		UAI_SPI_INIUART/SPI data in
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20MODE[2:0]DILMode [2]: select Host/Device bridge mode.
0: Device bridge mode.
1: Host bridge mode.
Mode [1:0]: select UDMA speed when FXDMA is set.
00: 100MB/s.
01: 133MB/s.
10: 150MB/s. (default)
11: Reserved.
MODE[1:0] must never be set to “11” and shall never be left floating!! External Pull resistor must be added!!		RSVDHDILReserved pin, it must be set to high.MODE[2]DILMode Selection:
Selection of the Host mode / Device mode.
0: Device mode (default)
1: Host mode		CFG0IDevice/Host mode enable
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19DIHMODE[1:0]DILUltra DMA operation rate.
Mode [1:0]: select UDMA speed when FXDMA is set.
00: 100MB/s.
01: 133MB/s.
10: 150MB/s. (default)
11: Reserved.
MODE[1:0] must never be set to “11” and shall never be left floating!! External Pull resistor must be added!!		MODE[1:0]DIHMode Selection: (for TEST)
For fixing a data transfer rate, also need to set FXDMA (38 pin).
00: 100MB/s
01: 133MB/s
10: 150MB/s (default)
11: Reserved (LSI test mode)		IDE_ORD_INVIATA Cable Signal Ordering Inverse
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18DILDIHDILD3V3_IOPWR3.3V Digital I/O Power
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33MSSELDIOLMaster/Slave Selection.
In Host Bridge mode:
0: Device 0 configuration. (default)
1: Device 1 configuration.
In Device Bridge mode, the pin is output (reserved).		RSVDLDILReserved pin, it must be set to low.MSSELDIOLMaster Slave Selection:
[Host mode: In, Device mode: Out]
- In the Host mode:
0: Master (default)
1: Slave (reserved)
- In the Device mode:
Data bit 4 of the Parallel ATA control register is output.		I_IDE_JUMP0IJumper 0
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38FXDMADILFixed UDMA Data Rate.
0: Adjustable Ultra DMA data rate according to SET FEATURE command (EFh).
1: Negate SET FEATURE command, and fix Ultra DMA data rate specified by MODE[1:0] setting.		FXDMADILFixed UDMA Data Rate.
0: Adjustable Ultra DMA data rate according to SET FEATURE command (EFh).
1: Negate SET FEATURE command, and fix Ultra DMA data rate specified by MODE[1:0] setting.		FXDMADILFixed UDMA Data Rate: (for TEST)
Forced setting of the transfer rate.
0: Settable by Set Feature command (default).
1: Fixed setting of the data transfer rate by MODE [1:0] (18,19 pin).		SPI_En_BOSPI Enable
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21ATAIOENDIHATA IO Interface Enable.
0: Disable the ATA output pins, present ATA I/O output pins are Hi-Z.
1: Enable the ATA output pins.		ATAIOENDIHATA IO Interface Enable.
0: Disable the ATA output pins, present ATA I/O output pins are Hi-Z.
1: Enable the ATA output pins.		ATAIOENDIHATA IO Interface Enable:
Forced setting of the Hi impedance output for ATA IO Pin.
0: Valid (Hi impedance mode)
1: Invalid (default)		UART_SPI_SELIUART/SPI interface enable
0: UART enable, 1: SPI enable
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39PMENDIHPower Management Command Enable. (reference 7.0)
0: Disable translating ATA Power Management feature command to Serial ATA Slumber mode.
1: Enable translating ATA Power Management feature command to Serial ATA Slumber mode.		PMENDIHPower Management Command Enable. (reference 7.0)
0: Disable translating ATA Power Management feature command to Serial ATA Slumber mode.
1: Enable translating ATA Power Management feature command to Serial ATA Slumber mode.		PMENDIHPower Management Command Enable:
Power saving mode setting for the Serial ATA by ATA Power Management Feature Setting command.
0: Invalid
1: Valid (default)		SPL_CLKOSPI Clock
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43UAIDIHOn-chip UART input used for internal debugging.UAIDIHOn-chip UART input used for internal debugging.UAIDIHOn-Chip UART InputI2C_SDAIOI2C Serial Data
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45UAODOHOn-chip UART output used for internal debugging.UAODOHOn-chip UART output used for internal debugging.UAODOHOn-Chip UART OutputI2C_SCLKIOI2C Serial Clock